1. Field of the Invention
The present invention relates to a power amplifier based on a voltage-coupling scheme, and more particularly to a power amplifier for use in a wireless communication system, in which two active elements are connected to each other via a primary part of a transformer, one of the two active elements is connected to a power-supply voltage of the power amplifier, the other one is connected to a ground terminal of the power amplifier, and an output power appears in a secondary part of the transformer, such that it decreases a potential difference between ports of the active elements, resulting in increased reliability of the power amplifier.
2. Description of the Related Art
Generally, the magnitude of output power of the power amplifier for use in a wireless communication system is proportional to the square of a power-supply voltage, and is inversely proportional to a load resistance value, as shown in the following Equation 1:
                              P          out                ∝                              V            DD            2                                R            load                                              [                  Equation          ⁢                                          ⁢          1                ]            
Therefore, a method for reproducing the load resistance value must be added to a method for acquiring the high output power. However, the above-mentioned method has difficulty in configuring an output matching circuit of a high-frequency power amplifier.
If the load resistance is decreased, total efficiency of the power amplifier is decreased as can be seen from the following Equation 2:
                    Efficiency        ∝                              R            load                                              R              load                        +                          R              on                                                          [                  Equation          ⁢                                          ⁢          2                ]            
In Equation 1, VDD is indicative of a power-supply voltage of the power-supply, and Rload is indicative of a load resistance value of the power amplifier.
In Equation 2, Ron is indicative of an ON-resistance value of the power element.
Therefore, the increasing of the power-supply voltage will be efficient for the high output power.
However, with the increasing demand of a high frequency circuit having a higher operation frequency, a fabrication process for the most general semiconductor element such as a CMOS has been continuously developed, resulting in implementation of the channel length of a sub-micron unit.
Due to the reduction of the channel length caused by the fabrication process, a breakdown voltage of the active element can also be lowered.
Generally, a power-supply voltage of a mobile phone is set to 3.3V. The highest voltage at a drain terminal (D) of the NMOS transistor 200 of the general power amplifier shown in FIG. 1 is equal to about three times the power-supply voltage.
FIG. 1 is a circuit diagram illustrating a power amplifier including a single NMOS according to a first example of the conventional art.
The breakdown voltage is about 5V in consideration of the NMOS based on the CMOS-0.18 μm fabrication process, such that a general power amplifier shown in FIG. 1 can be made unavailable under the condition of the power-supply voltage 3.3V.
In order to solve the above-mentioned problem, there is proposed a cascode structure shown in FIG. 2.
FIG. 2 is a circuit diagram illustrating a power amplifier in which a cascode structure is implemented by two NMOS transistors according to a second example of the conventional art.
The cascode structure has been widely used as a general structure. A representative cascode structure has been disclosed in the paper, entitled “A 900 MHz GSM PA in 250 nm CMOS with Breakdown Voltage Protection and Programmable Conduction Angle”, and filed by K. Choi, D. J. Allstot, and Krishnamurthy, in IEEE RFIC Symposium, pp. 359-372, June 2004.
As shown in FIG. 2, provided that a first NMOS transistor 201 is connected to a second NMOS transistor 202, although the highest voltage condition of about 10V is provided at a drain terminal D of the first NMOS transistor 201, the first NMOS transistor 201 copes with 5V and the second NMOS transistor 202 copes with 5V, such that individual elements do not reach the breakdown voltage, and the power amplifier can be normally operated.
However, according to the above-mentioned method, the second NMOS transistor 202 is designed to amplify the input signal, and the first NMOS transistor 201 is designed to undergo a high drain voltage.
The ON resistance value of the first NMOS transistor 201 is added to that of the second NMOS transistor 202, such that overall efficiency of the power amplifier is decreased as shown in Equation 2.
In the meantime, a power-supply voltage of a battery of a mobile phone increases to 4.2V after the battery is completely charged with electricity. In this case, the power amplifier of FIG. 2 is unable to endure the high drain voltage, such that an element breakdown and a deterioration of reliability of the power-supply are generated.
In order to solve the above-mentioned element breakdown problem, another conventional art shown in FIG. 3 may also be introduced to the market.
FIG. 3 is a circuit diagram illustrating a power amplifier in which three NMOS transistors are connected according to a third example of the conventional art.
However, since the power amplifier of FIG. 3 interconnects NMOS transistors 203, 204, and 205 acting as active elements in series to each other, the ON resistance value caused by the serial connection of the above NMOS transistors 203, 204, and 205 unavoidably increases, such that overall efficiency of the power-supply is lowered.
In conclusion, the above-mentioned conventional arts have difficulty in implementing a power amplifier capable of being normally operated simultaneously while acquiring high efficiency at a high power-supply voltage.